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feb . '00 mitsubishi lsis mitsubishi electric sdram (rev.3.2) 64 m synchronous dram m2v64s20dtp-6,-6l,-7,-7l,-8,-8l (4-bank x 4,194,304 -word x 4-bit) (4-bank x 2,097,152-word x 8-bit) (4-bank x 1,048,576 -word x 16-bit) m2v64s30dtp-6,-6l,-7,-7l,-8,-8l m2v64s40dtp-6,-6l,-7,-7l,-8,-8l 1 m2v64s20dtp is a 4-bank x 4,194,304-word x 4-bit, m2v64s30dtp is a 4-bank x 2,097,152-word x 8-bit, m2v64s40dtp is a 4-bank x 1,048,576-word x 16-bit, synchronous dram, with lvttl interface. all inputs and outputs are referenced to the rising edge of clk. m2v64s20dtp, m2v64s30dtp and m2v64s40dtp achieve very high speed data rate up to 133mhz for -6, and are suitable for main memory or graphic memory in computer systems. - single 3.3v0.3v power supply - max. clock frequency -6:133mhz<3-3-3>, -7:100mhz<2-2-2>, -8:100mhz<3-2-2> - fully synchronous operation referenced to clock rising edge - 4 bank operation controlled by ba0 & ba1 (bank address) - /cas latency- 2 and 3 (programmable) - burst length- 1, 2, 4, 8 and full page (programmable) - burst type- sequential and interleave (programmable) - byte control- dqml and dqmu for m2v64s40dtp - random column access - auto precharge and all bank precharge controlled by a10 - auto refresh and self refresh - 4096 refresh cycles every 64ms - lvttl interface - 400-mil, 54-pin thin small outline package (tsop ii) with 0.8mm lead pitch description features preliminary some of contents are described for general products and are subject to change without notice. item tclk m2v64s20/30/40dtp -7 -8 tras trcd tac trc icc1 icc6 clock cycle time (min.) active to precharge command period (min.) row to column delay (min.) access time from clk (max.) (cl=3) ref /active command period (min.) operation current (max.) (single bank) self refresh current (max.) 10 ns 50 ns 20ns 6ns 70ns 1 ma 10ns 50ns 20ns 6ns 70ns 1 ma v64s20d v64s30d v64s40d -6 7.5 ns 45 ns 20ns 5.4 ns 67.5 ns 1 ma 70ma 70ma 80ma 70ma 70ma 80ma 75ma 75ma 85ma
feb . '00 mitsubishi lsis mitsubishi electric sdram (rev.3.2) 64 m synchronous dram m2v64s20dtp-6,-6l,-7,-7l,-8,-8l (4-bank x 4,194,304 -word x 4-bit) (4-bank x 2,097,152-word x 8-bit) (4-bank x 1,048,576 -word x 16-bit) m2v64s30dtp-6,-6l,-7,-7l,-8,-8l m2v64s40dtp-6,-6l,-7,-7l,-8,-8l 2 pin configuration (top view) m2v64s30dtp m2v64s40dtp pin configuration (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 23 32 24 31 25 30 26 29 27 28 vdd dq0 vddq dq1 dq2 vssq dq3 dq4 vddq dq5 dq6 vssq dq7 vdd dqml /we /cas /ras /cs ba0(a13) ba1(a12) a10(ap) a2 a3 vdd a0 a1 vss dq15 vssq dq14 dq13 vddq dq12 dq11 vssq dq10 dq9 vddq dq8 vss nc dqmu clk cke nc a11 a8 a7 a6 a5 a4 vss a9 vdd dq0 vddq nc dq1 vssq nc dq2 vddq nc dq3 vssq nc vdd nc /we /cas /ras /cs ba0(a13) ba1(a12) a10(ap) a2 a3 vdd a0 a1 vdd nc vddq nc dq0 vssq nc nc vddq nc dq1 vssq nc vdd nc /we /cas /ras /cs ba0(a13) ba1(a12) a10(ap) a2 a3 vdd a0 a1 vss dq7 vssq nc dq6 vddq nc dq5 vssq nc dq4 vddq nc vss nc dqm clk cke nc a11 a8 a7 a6 a5 a4 vss a9 vss nc vssq nc dq3 vddq nc nc vssq nc dq2 vddq nc vss nc dqm clk cke nc a11 a8 a7 a6 a5 a4 vss a9 m2v64s20dtp clk : master clock cke : clock enable /cs : chip select /ras : row address strobe /cas : column address strobe /we : write enable dq0-15 : data i/o dqm : output disable/ write mask a0-11 : address input ba0,1 : bank address vdd : power supply vddq : power supply for output vss : ground vssq : ground for output
feb . '00 mitsubishi lsis mitsubishi electric sdram (rev.3.2) 64 m synchronous dram m2v64s20dtp-6,-6l,-7,-7l,-8,-8l (4-bank x 4,194,304 -word x 4-bit) (4-bank x 2,097,152-word x 8-bit) (4-bank x 1,048,576 -word x 16-bit) m2v64s30dtp-6,-6l,-7,-7l,-8,-8l m2v64s40dtp-6,-6l,-7,-7l,-8,-8l 3 block diagram type designation code m2 v 64 s 3 0 tp -8 access item package type process generation interface organization synchronous dram density function mitsubishi dram these rules are only applied to the synchronous dram family. note : this figure shows the m2v64s30dtp. the m2v64s20dtp configration is 4096x1024x4 of cell array and dq 0-3. the m2v64s40dtp configration is 4096x256x16 of cell array and dq 0-15. address buffer a0-11 ba0,1 control signal buffer /cs /ras /cas /we clk cke clock buffer control circuitry i/o buffer dq0-7 mode register dqm memory array bank #0 4096 x512 x8 cell array memory array bank #1 4096 x512 x8 cell array memory array bank #2 4096 x512 x8 cell array memory array bank #3 4096 x512 x8 cell array d -6 : 7.5ns (pc133 3-3-3), -7 : 10ns (pc100 2-2-2), -8 : 10ns (pc100 3-2-2) tp: tsop(ii) d : 5th gen. reserved for future use 2 : x4, 3 : x8, 4 : x16 64 : 64mbit v : lvttl
feb . '00 mitsubishi lsis mitsubishi electric sdram (rev.3.2) 64 m synchronous dram m2v64s20dtp-6,-6l,-7,-7l,-8,-8l (4-bank x 4,194,304 -word x 4-bit) (4-bank x 2,097,152-word x 8-bit) (4-bank x 1,048,576 -word x 16-bit) m2v64s30dtp-6,-6l,-7,-7l,-8,-8l m2v64s40dtp-6,-6l,-7,-7l,-8,-8l 4 pin function clk input master clock: all other inputs are referenced to the rising edge of clk. cke input clock enable: cke controls internal clock. when cke is low, internal clock for the following cycle is ceased. cke is also used to select auto / selfrefresh. after self refresh mode is started, cke becomes asynchronous input. self refresh is maintained as long as cke is low. /cs input chip select: when /cs is high, any command means no operation. /ras, /cas, /we input combination of /ras, /cas, /we defines basic commands. a0-11 input a0-11 specify the row / column address in conjunction with ba0,1. the row address is specified by a0-11. the column address is specified by a0-9 (x4) / a0-8 (x8) / a0-7 (x16). a10 is also used to indicate precharge option. when a10 is high at a read / write command, an auto precharge is performed. when a10 is high at a precharge command, all banks are precharged. ba0,1 input bank address: ba0,1 specifies one of four banks to which a command is applied. ba0,1 must be set with act, pre, read, write commands. input / output input din mask and output disable: when dqm(u, l) is high in burst write, din for the current cycle is masked. when dqm(u, l) is high in burst read, dout is disabled at the next but one cycle. vdd, vss power supply power supply for the memory array and peripheral circuitry. vddq, vssq power supply vddq and vssq are supplied to the output buffers only. data in and data out are referenced to the rising edge of clk. dq0-3(x4), dq0-7(x8), dq0-15(x16) dqm(x4,x8), dqm(u, l)(x16)
feb . '00 mitsubishi lsis mitsubishi electric sdram (rev.3.2) 64 m synchronous dram m2v64s20dtp-6,-6l,-7,-7l,-8,-8l (4-bank x 4,194,304 -word x 4-bit) (4-bank x 2,097,152-word x 8-bit) (4-bank x 1,048,576 -word x 16-bit) m2v64s30dtp-6,-6l,-7,-7l,-8,-8l m2v64s40dtp-6,-6l,-7,-7l,-8,-8l 5 basic functions the m2v64s20, 30 and 40dtp provides basic functions, bank (row) activate, burst read and write, bank (row) precharge, and auto and self refresh. each command is defined by control signals of /ras, /cas and /we at clk rising edge. in addition to 3 signals, /cs ,cke and a10 are used as chip select, refresh option, and precharge option, respectively. to know the detailed definition of commands, please see the command truth table. activate (act) [/ras =l, /cas =/we =h] act command activates a row in an idle bank indicated by ba. read (read) [/ras =h, /cas =l, /we =h] read command starts burst read from the active bank indicated by ba. first output data appears after /cas latency. when a10 =h at this command, the bank is deactivated after the burst read (auto- precharge, reada ) write (write) [/ras =h, /cas =/we =l] write command starts burst write to the active bank indicated by ba. total data length to be written is set by burst length. when a10 =h at this command, the bank is deactivated after the burst write (auto-precharge, writea ). precharge (pre) [/ras =l, /cas =h, /we =l] pre command deactivates the active bank indicated by ba. this command also terminates burst read /write operation. when a10 =h at this command, all banks are deactivated (precharge all, prea ). auto-refresh (refa) [/ras =/cas =l, /we =cke =h] refa command starts auto-refresh cycle. refresh address are generated internally. after this command, the banks are precharged automatically. /cs chip select : l=select, h=deselect /ras command /cas command /we command cke refresh option @refresh command a10 precharge option @precharge or read/write command clk define basic commands
feb . '00 mitsubishi lsis mitsubishi electric sdram (rev.3.2) 64 m synchronous dram m2v64s20dtp-6,-6l,-7,-7l,-8,-8l (4-bank x 4,194,304 -word x 4-bit) (4-bank x 2,097,152-word x 8-bit) (4-bank x 1,048,576 -word x 16-bit) m2v64s30dtp-6,-6l,-7,-7l,-8,-8l m2v64s40dtp-6,-6l,-7,-7l,-8,-8l 6 command truth table h=high level, l=low level, v=valid, x=don't care, n=clk cycle number note: 1. a7-a9 =0, a0-a6 =mode address command mnemonic cke n-1 cke n /cs /ras /cas /we ba0,1 a11 a10 a0-9 deselect desel h x h x x x x x x x no operation nop h x l h h h x x x x row address entry & bank activate act h x l l h h v v v v single bank precharge pre h x l l h l v x l x precharge all banks prea h x l l h l x h x column address entry & write write h x l h l l v v l v column address entry & write with auto-precharge writea h x l h l l v v h v column address entry & read read h x l h l h v v l v column address entry & read with auto-precharge reada h x l h l h v v h v auto-refresh refa h h l l l h x x x x self-refresh entry refs h l l l l h x x x x self-refresh exit refsx l h h x x x x x x x l h l h h h x x x x mode register set mrs h x l l l l l l l v*1 x burst terminate tbst h x l h h l x x x x
feb . '00 mitsubishi lsis mitsubishi electric sdram (rev.3.2) 64 m synchronous dram m2v64s20dtp-6,-6l,-7,-7l,-8,-8l (4-bank x 4,194,304 -word x 4-bit) (4-bank x 2,097,152-word x 8-bit) (4-bank x 1,048,576 -word x 16-bit) m2v64s30dtp-6,-6l,-7,-7l,-8,-8l m2v64s40dtp-6,-6l,-7,-7l,-8,-8l 7 h x x x x desel nop l h h h x nop nop l h h l x tbst illegal*2 l h l x ba, ca, a10 read & write illegal*2 l l h h ba, ra act bank active, latch ra l l h l ba, a10 pre & prea nop*4 l l l h x refa auto-refresh*5 l l l l op-code, mode-add mrs mode register set*5 h x x x x desel nop l h h h x nop nop l h h l x tbst nop l h l h ba, ca, a10 read & reada begin read, latch ca, determine auto-precharge l h l l ba, ca, a10 write & writea begin write, latch ca, determine auto-precharge l l h h ba, ra act bank active / illegal*2 l l h l ba, a10 pre & prea precharge / precharge all l l l h x refa illegal l l l l op-code, mode-add mrs illegal function truth table current state /cs /ras /cas /we address command action idle row active
feb . '00 mitsubishi lsis mitsubishi electric sdram (rev.3.2) 64 m synchronous dram m2v64s20dtp-6,-6l,-7,-7l,-8,-8l (4-bank x 4,194,304 -word x 4-bit) (4-bank x 2,097,152-word x 8-bit) (4-bank x 1,048,576 -word x 16-bit) m2v64s30dtp-6,-6l,-7,-7l,-8,-8l m2v64s40dtp-6,-6l,-7,-7l,-8,-8l 8 current state /cs /ras /cas /we address command action function truth table (continued) read write l h h l x tbst terminate burst l h l h ba, ca, a10 read /reada terminate burst, latch ca, begin new read, determine auto-precharge*3 l h l l ba, ca, a10 write & writea terminate burst, latch ca, begin write, determine auto-precharge*3 l l h l ba, a10 pre & prea terminate burst, precharge l l l h x refa illegal l l l l op-code, mode-add mrs illegal h x x x x desel nop (continue burst to end) l h h h x nop nop (continue burst to end) l l h h ba, ra act bank active / illegal*2 h x x x x desel nop (continue burst to end) l h h h x nop nop (continue burst to end) l h h l x tbst terminate burst l h l h ba, ca, a10 read & reada terminate burst, latch ca, begin read, determine auto-precharge*3 l h l l ba, ca, a10 write & writea terminate burst, latch ca,begin write, determine auto-precharge*3 l l h h ba, ra act bank active / illegal*2 l l h l ba, a10 pre & prea terminate burst, precharge l l l h x refa illegal l l l l mrs illegal op-code, mode-add
feb . '00 mitsubishi lsis mitsubishi electric sdram (rev.3.2) 64 m synchronous dram m2v64s20dtp-6,-6l,-7,-7l,-8,-8l (4-bank x 4,194,304 -word x 4-bit) (4-bank x 2,097,152-word x 8-bit) (4-bank x 1,048,576 -word x 16-bit) m2v64s30dtp-6,-6l,-7,-7l,-8,-8l m2v64s40dtp-6,-6l,-7,-7l,-8,-8l 9 current state /cs /ras /cas /we address command action function truth table (continued) read with auto precharge h x x x x desel nop (continue burst to end) l h h h x nop nop (continue burst to end) l h h l x tbst illegal l h l h ba, ca, a10 read & reada illegal l h l l ba, ca, a10 write & writea illegal l l h h ba, ra act bank active / illegal*2 l l h l ba, a10 pre & prea illegal*2 l l l h x refa illegal l l l l op-code, mode-add mrs illegal write with auto precharge h x x x x desel nop (continue burst to end) l h h h x nop nop (continue burst to end) l h h l x tbst illegal l h l h ba, ca, a10 read & reada illegal l h l l ba, ca, a10 write & writea illegal l l h h ba, ra act bank active / illegal*2 l l h l ba, a10 pre & prea illegal*2 l l l h x refa illegal l l l l op-code, mode-add mrs illegal
feb . '00 mitsubishi lsis mitsubishi electric sdram (rev.3.2) 64 m synchronous dram m2v64s20dtp-6,-6l,-7,-7l,-8,-8l (4-bank x 4,194,304 -word x 4-bit) (4-bank x 2,097,152-word x 8-bit) (4-bank x 1,048,576 -word x 16-bit) m2v64s30dtp-6,-6l,-7,-7l,-8,-8l m2v64s40dtp-6,-6l,-7,-7l,-8,-8l 10 current state /cs /ras /cas /we address command action function truth table (continued) pre - charging row activating h x x x x desel nop (idle after trp) l h h h x nop nop (idle after trp) l h h l x tbst illegal*2 l h l x ba, ca, a10 read & write illegal*2 l l h h ba, ra act illegal*2 l l h l ba, a10 pre & prea nop*4 (idle after trp) l l l h x refa illegal l l l l op-code, mode-add mrs illegal h x x x x desel nop (row active after trcd) l h h h x nop nop (row active after trcd) l h h l x tbst illegal*2 l h l x ba, ca, a10 read & write illegal*2 l l h h ba, ra act illegal*2 l l h l ba, a10 pre & prea illegal*2 l l l h x refa illegal l l l l op-code, mode-add mrs illegal
feb . '00 mitsubishi lsis mitsubishi electric sdram (rev.3.2) 64 m synchronous dram m2v64s20dtp-6,-6l,-7,-7l,-8,-8l (4-bank x 4,194,304 -word x 4-bit) (4-bank x 2,097,152-word x 8-bit) (4-bank x 1,048,576 -word x 16-bit) m2v64s30dtp-6,-6l,-7,-7l,-8,-8l m2v64s40dtp-6,-6l,-7,-7l,-8,-8l 11 current state /cs /ras /cas /we address command action function truth table (continued) h x x x x desel nop write recovering l h h h x nop nop l h h l x tbst illegal*2 l h l x ba, ca, a10 read & write illegal*2 l l h h ba, ra act illegal*2 l l h l ba, a10 pre & prea illegal*2 l l l h x refa illegal l l l l op-code, mode-add mrs illegal refreshing h x x x x desel nop (idle after trc) l h h h x nop nop (idle after trc) l h h l x tbst illegal l h l x ba, ca, a10 read & write illegal l l h h ba, ra act illegal l l h l ba, a10 pre & prea illegal l l l h x refa illegal l l l l op-code, mode-add mrs illegal
feb . '00 mitsubishi lsis mitsubishi electric sdram (rev.3.2) 64 m synchronous dram m2v64s20dtp-6,-6l,-7,-7l,-8,-8l (4-bank x 4,194,304 -word x 4-bit) (4-bank x 2,097,152-word x 8-bit) (4-bank x 1,048,576 -word x 16-bit) m2v64s30dtp-6,-6l,-7,-7l,-8,-8l m2v64s40dtp-6,-6l,-7,-7l,-8,-8l 12 mode register setting h x x x x desel nop (idle after trsc) l h h h x nop nop (idle after trsc) l h h l x tbst illegal l h l x ba, ca, a10 read & write illegal l l h h ba, ra act illegal l l h l ba, a10 pre & prea illegal l l l h x refa illegal l l l l op-code, mode-add mrs illegal abbreviations: h=high level, l=low level, x=don't care ba=bank address, ra=row address, ca=column address, nop=no operation notes: 1. all entries assume that cke was high during the preceding clock cycle and the current clock cycle. 2. illegal to bank in specified state; function may be legal in the bank indicated by ba, depending on the state of that bank. 3. must satisfy bus contention, bus turn around, write recovery requirements. 4. nop to bank precharging or in idle state. may precharge bank indicated by ba. 5. illegal if any bank is not idle. illegal = device operation and/or data-integrity are not guaranteed. current state /cs /ras /cas /we address command action function truth table (continued)
feb . '00 mitsubishi lsis mitsubishi electric sdram (rev.3.2) 64 m synchronous dram m2v64s20dtp-6,-6l,-7,-7l,-8,-8l (4-bank x 4,194,304 -word x 4-bit) (4-bank x 2,097,152-word x 8-bit) (4-bank x 1,048,576 -word x 16-bit) m2v64s30dtp-6,-6l,-7,-7l,-8,-8l m2v64s40dtp-6,-6l,-7,-7l,-8,-8l 13 function truth table for cke current state cke n-1 cke n /cs /ras /cas /we add action self- refresh*1 h x x x x x x invalid l h h x x x x exit self-refresh (idle after trc) l h l h h h x exit self-refresh (idle after trc) l h l h h l x illegal l h l h l x x illegal l h l l x x x illegal l l x x x x x nop (maintain self-refresh) power down h x x x x x x invalid l h x x x x x exit power down to idle l l x x x x x nop (maintain power down) all banks idle*2 h h x x x x x refer to function truth table h l l l l h x enter self-refresh h l h x x x x enter power down h l l h h h x enter power down h l l h h l x illegal h l l h l x x illegal h l l l x x x illegal l x x x x x x refer to current state =power down any state other than listed above h h x x x x x refer to function truth table h l x x x x x begin clk suspend at next cycle*3 l h x x x x x exit clk suspend at next cycle*3 l l x x x x x maintain clk suspend abbreviations: h=high level, l=low level, x=don't care notes: 1. cke low to high transition will re-enable clk and other inputs asynchronously . a minimum setup time must be satisfied before any command other than exit. 2. power-down and self-refresh can be entered only from the all banks idle state. 3. must be legal command.
feb . '00 mitsubishi lsis mitsubishi electric sdram (rev.3.2) 64 m synchronous dram m2v64s20dtp-6,-6l,-7,-7l,-8,-8l (4-bank x 4,194,304 -word x 4-bit) (4-bank x 2,097,152-word x 8-bit) (4-bank x 1,048,576 -word x 16-bit) m2v64s30dtp-6,-6l,-7,-7l,-8,-8l m2v64s40dtp-6,-6l,-7,-7l,-8,-8l 14 simplified state diagram ckel ckeh ckel ckeh ckel ckeh ckel ckeh act refa refs refsx ckel ckeh mrs ckel ckeh write read writea writea reada write read pre reada writea reada pre pre pre power applied automatic sequence command sequence self refresh auto refresh idle power down mode register set clk suspend row active write read reada pre charge writea power on write suspend writea suspend reada suspend read suspend term term
feb . '00 mitsubishi lsis mitsubishi electric sdram (rev.3.2) 64 m synchronous dram m2v64s20dtp-6,-6l,-7,-7l,-8,-8l (4-bank x 4,194,304 -word x 4-bit) (4-bank x 2,097,152-word x 8-bit) (4-bank x 1,048,576 -word x 16-bit) m2v64s30dtp-6,-6l,-7,-7l,-8,-8l m2v64s40dtp-6,-6l,-7,-7l,-8,-8l 15 power on sequence before starting normal operation, the following power on sequence is necessary to prevent a sdram from damaged or malfunctioning. 1. apply power and start clock. attempt to maintain cke high, dqm high and nop condition at the inputs. 2. maintain stable power, stable clock, and nop input conditions for a minimum of 200s. 3. issue precharge commands for all banks. (pre or prea) 4. after all banks become idle state (after trp), issue 8 or more auto-refresh commands. 5. issue a mode register set command to initialize the mode register. after these sequence, the sdram is idle state and ready for normal operation. mode register burst length, burst type, /cas latency and write mode can be programmed by setting the mode register (mrs). the mode register stores these data until the next mrs command, which may be issued when both banks are in idle state. after trsc from a mrs command, the sdram is ready for new command. /cs /ras /cas /we ba0,1 a11-a0 clk v r: reserved for future use ba0 ba1 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 0 0 0 0 wm 0 0 ltmode bt bl burst length bl bt=0 bt=1 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 1 2 4 8 r r r full page 1 2 4 8 r r r r 0 1 burst type sequential interleaved latency mode cl /cas latency 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 r r 2 3 r r r r burst write single write write mode 0 1
feb . '00 mitsubishi lsis mitsubishi electric sdram (rev.3.2) 64 m synchronous dram m2v64s20dtp-6,-6l,-7,-7l,-8,-8l (4-b a nk x 4,194,304 -word x 4-bit) (4-b a nk x 2,097,152-word x 8-bit) (4-b a nk x 1,048,576 -word x 16-bit) m2v64s30dtp-6,-6l,-7,-7l,-8,-8l m2v64s40dtp-6,-6l,-7,-7l,-8,-8l 16 a2 a1 a0 initial addre ss bl sequential interleaved column addre ss ing 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 - 0 0 - 0 1 - 1 0 - 1 1 - - 0 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 1 2 3 4 5 6 7 0 1 0 3 2 5 4 7 6 2 3 4 5 6 7 0 1 2 3 0 1 6 7 4 5 3 4 5 6 7 0 1 2 3 2 1 0 7 6 5 4 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 5 6 7 0 1 2 3 4 5 4 7 6 1 0 3 2 6 7 0 1 2 3 4 5 6 7 4 5 2 3 0 1 7 0 1 2 0 1 2 3 1 2 3 0 2 3 0 1 3 0 0 1 7 6 5 4 0 1 2 3 1 0 3 2 2 3 0 1 3 2 0 1 - - 1 1 2 1 0 3 4 5 6 3 2 1 0 1 0 1 0 8 4 2 command addre ss clk read y write y /cas latency bur s t length bur s t length dq bur s t type cl= 3 bl= 4 q0 q1 q2 q3 d0 d1 d2 d3
feb . '00 mitsubishi lsis mitsubishi electric sdram (rev.3.2) 64 m synchronous dram m2v64s20dtp-6,-6l,-7,-7l,-8,-8l (4-bank x 4,194,304 -word x 4-bit) (4-bank x 2,097,152-word x 8-bit) (4-bank x 1,048,576 -word x 16-bit) m2v64s30dtp-6,-6l,-7,-7l,-8,-8l m2v64s40dtp-6,-6l,-7,-7l,-8,-8l 17 operational description bank activate one of four banks is activated by an act command. an bank is selected by ba0-1. a row is selected by a0-1 1 . multiple banks can be active state concurrently by issuing multiple act commands. minimum activation interval between one bank and another bank is trrd. precharge an open bank is deactivated by a pre command. a bank to be deactivated is designated by ba0-1. when multiple banks are active, a precharge all command (prea, pre + a10=h) deactivates all of open banks at the same time. ba0-1 are "don't care" in this case. minimum delay of an act command after a pre command to the same bank is trp. read a read command can be issued to any active bank. the start address is specified by a0-9(x4), a0-8 (x8), a0-7 (x16). 1st output data is available after the /cas latency from the read. the consecutive data length is defined by the burst length. the address sequence of the burst data is defined by the burst type. minimum delay of a read command after an act command to the same bank is trcd. when a10 is high at a read command, auto-precharge (reada) is performed. any command (read, write, pre, act,tbst) to the same bank is inhibited till the internal precharge is complete. the internal precharge starts at the bl after reada. the next act command can be issued after (bl + trp) from the previous reada. in any case, trcd+bl > trasmin must be met. bank activation and precharge all (bl=4, cl=2) clk command a0-9,11 a10 ba0-1 dq act read act pre act xa xb y b xa 1 xa xb 0 00 01 01 00 qb0 qb1 qb2 qb3 trrd trcd trp xa precharge all =
feb . '00 mitsubishi lsis mitsubishi electric sdram (rev.3.2) 64 m synchronous dram m2v64s20dtp-6,-6l,-7,-7l,-8,-8l (4-bank x 4,194,304 -word x 4-bit) (4-bank x 2,097,152-word x 8-bit) (4-bank x 1,048,576 -word x 16-bit) m2v64s30dtp-6,-6l,-7,-7l,-8,-8l m2v64s40dtp-6,-6l,-7,-7l,-8,-8l 18 clk command a0-9,11 a10 ba0-1 dq act act xa xa xa 00 00 trcd trp xa read with auto-precharge (cl=2, bl=4) read y a 1 00 qa0 qa1 qa2 qa3 i nternal precharge starts bl clk command dq act act trcd auto-precharge timing (read, bl=4) read qa0 qa1 qa2 qa3 i nternal precharge starts bl dq qa0 qa1 qa2 qa3 cl=2 cl=3 clk command a0-9,11 a10 ba0-1 dq act read act pre act xa xb y b xa 0 xa xb 0 00 01 01 00 qb0 qb1 qb2 qb3 trcd trcd trp xa multi bank interleaving read (cl=2, bl=4) read y a 0 00 qa0 qa1 qa2 qa3 00
feb . '00 mitsubishi lsis mitsubishi electric sdram (rev.3.2) 64 m synchronous dram m2v64s20dtp-6,-6l,-7,-7l,-8,-8l (4-bank x 4,194,304 -word x 4-bit) (4-bank x 2,097,152-word x 8-bit) (4-bank x 1,048,576 -word x 16-bit) m2v64s30dtp-6,-6l,-7,-7l,-8,-8l m2v64s40dtp-6,-6l,-7,-7l,-8,-8l 19 write a write command can be issued to any active bank.the start address is specified by a0-9(x4), a0-8 (x8), a0-7 (x16). 1st input data is set at the same cycle as the write. the consecutive data length to be written is defined by the burst length. the address sequence of burst data is defined by the burst type. minimum delay of a write command after an act command to the same bank is trcd. from the last input data to the pre command, the write recovery time (twr) is required. when a10 is high at a write command, auto-precharge (writea) is performed. any command (read, write, pre, act, tbst) to the same bank is inhibited till the internal precharge is complete. the internal precharge starts at twr after the last input data cycle. the next act command can be issued after (bl + twr -1 +trp) from the previous writea. in any case, trcd + bl + twr -1 > trasmin must be met. clk command a0-9,11 a10 ba0-1 dq act pre act xa xa 0 xa 00 00 trcd trp xa write (bl=4) write y a 0 00 d a0 d a1 d a2 d a3 bl twr clk command a0-9,11 a10 ba0-1 dq act act xa xa xa 00 00 trcd trp xa write with auto-precharge (bl=4) write y a 1 00 d a0 d a1 d a2 d a3 bl twr internal precharge starts = 00
feb . '00 mitsubishi lsis mitsubishi electric sdram (rev.3.2) 64 m synchronous dram m2v64s20dtp-6,-6l,-7,-7l,-8,-8l (4-bank x 4,194,304 -word x 4-bit) (4-bank x 2,097,152-word x 8-bit) (4-bank x 1,048,576 -word x 16-bit) m2v64s30dtp-6,-6l,-7,-7l,-8,-8l m2v64s40dtp-6,-6l,-7,-7l,-8,-8l 20 burst interruption [ read interrupted by read ] burst read operation can be interrupted by new read of any active bank. random column access is allowed. read to read interval is minimum 1 clk. [ read interrupted by write ] burst read operation can be interrupted by write of any active bank. random column access is allowed. in this case, the dq should be controlled adequately by using the dqm to prevent the bus contention. the output is disabled automatically 1 cycle after write assertion. clk command a0-9,11 a10 ba0-1 dq read y b 0 0 0 qc0 qc1 qc2 qc3 read interrupted by read (cl=2, bl=4) read y a 0 00 qa0 qa1 qa2 qb0 read y c 0 1 0 clk command a0-9,11 a10 ba0-1 dq act xa xa 00 read interrupted by write (cl=2, bl=4) read y a 0 00 qa0 d a0 d a1 d a2 dqm write y a 0 00 d a3 output disable by dqm by write
feb . '00 mitsubishi lsis mitsubishi electric sdram (rev.3.2) 64 m synchronous dram m2v64s20dtp-6,-6l,-7,-7l,-8,-8l (4-bank x 4,194,304 -word x 4-bit) (4-bank x 2,097,152-word x 8-bit) (4-bank x 1,048,576 -word x 16-bit) m2v64s30dtp-6,-6l,-7,-7l,-8,-8l m2v64s40dtp-6,-6l,-7,-7l,-8,-8l 21 [ read interrupted by precharge ] a burst read operation can be interrupted by a precharge of the same bank . read to pre interval is minimum 1 clk. a pre command to output disable latency is equivalent to the /cas latency. read interrupted by precharge (bl=4) clk command dq pre read q0 q1 q2 command dq pre read q0 q1 command dq pre read q0 command dq pre read q0 q1 q2 command dq pre read q0 q1 command dq pre read q0 cl=2 cl=3
feb . '00 mitsubishi lsis mitsubishi electric sdram (rev.3.2) 64 m synchronous dram m2v64s20dtp-6,-6l,-7,-7l,-8,-8l (4-bank x 4,194,304 -word x 4-bit) (4-bank x 2,097,152-word x 8-bit) (4-bank x 1,048,576 -word x 16-bit) m2v64s30dtp-6,-6l,-7,-7l,-8,-8l m2v64s40dtp-6,-6l,-7,-7l,-8,-8l 22 [ read interrupted by burst terminate ] similarly to the precharge, a burst terminate command can interrupt the burst read operation and disable the data output. the terminated bank remains active. read to tbst interval is minimum 1 clk. a tbst command to output disable latency is equivalent to the /cas latency. clk command dq tbst read q0 q1 q2 command dq tbst read q0 q1 command dq tbst read q0 command dq tbst read q0 q1 q2 command dq tbst read q0 q1 command dq tbst read q0 cl=2 cl=3 read interrupted by terminate (bl=4)
feb . '00 mitsubishi lsis mitsubishi electric sdram (rev.3.2) 64 m synchronous dram m2v64s20dtp-6,-6l,-7,-7l,-8,-8l (4-bank x 4,194,304 -word x 4-bit) (4-bank x 2,097,152-word x 8-bit) (4-bank x 1,048,576 -word x 16-bit) m2v64s30dtp-6,-6l,-7,-7l,-8,-8l m2v64s40dtp-6,-6l,-7,-7l,-8,-8l 23 [ write interrupted by write ] burst write operation can be interrupted by new write of any active bank. random column access is allowed. write to write interval is minimum 1 clk. [ write interrupted by read ] burst write operation can be interrupted by read of any active bank. random column access is allowed. write to read interval is minimum 1 clk. the input data on dq at the interrupting read cycle is "don't care". write interrupted by write (bl=4) clk command a0-9,11 a10 ba0-1 dq write y b 0 0 0 d c 0 d c 1 d c 2 d c 3 write y a 0 00 d a0 d a1 d a2 d b 0 write y c 0 10 clk command a0-9,11 a10 ba0-1 dq act xa xa 00 write interrupted by read (cl=2, bl=4) read y b 0 00 d a0 d a1 qb0 write y a 0 00 qb1 qb2 qb3 don't care
feb . '00 mitsubishi lsis mitsubishi electric sdram (rev.3.2) 64 m synchronous dram m2v64s20dtp-6,-6l,-7,-7l,-8,-8l (4-bank x 4,194,304 -word x 4-bit) (4-bank x 2,097,152-word x 8-bit) (4-bank x 1,048,576 -word x 16-bit) m2v64s30dtp-6,-6l,-7,-7l,-8,-8l m2v64s40dtp-6,-6l,-7,-7l,-8,-8l 24 [ write interrupted by precharge ] burst write operation can be interrupted by precharge of the same bank. write recovery time (twr) is required from the last data to pre command. during write recovery, data inputs must be masked by dqm. [ write interrupted by burst terminate ] burst terminate command can terminate burst write operation. in this case, the write recovery time is not required and the bank remains active. write to tbst interval is minimum 1 clk. clk command a0-9,11 a10 ba0-1 dq write y a 0 0 0 write interrupted by precharge (bl=4) act x a 0 00 d a0 d a1 pre 0 00 act x a 0 00 twr trp dqm clk command a0-9,11 a10 ba0-1 dq write y a 0 0 0 write interrupted by terminate (bl=4) act x a 0 00 d a0 d a1 tbst write y b 0 0 0 d b 0 d b 1 d b 2 d b 3
feb . '00 mitsubishi lsis mitsubishi electric sdram (rev.3.2) 64 m synchronous dram m2v64s20dtp-6,-6l,-7,-7l,-8,-8l (4-bank x 4,194,304 -word x 4-bit) (4-bank x 2,097,152-word x 8-bit) (4-bank x 1,048,576 -word x 16-bit) m2v64s30dtp-6,-6l,-7,-7l,-8,-8l m2v64s40dtp-6,-6l,-7,-7l,-8,-8l 25 [ write with auto-precharge interrupted by write or read to another bank ] burst write with auto-precharge can be interrupted by write or read to a nother bank . next act comand can be issued after (bl+twr-1+trp) from the writea. auto-precharge interruption by a command to the same bank is inhibited. writea interrupted by write to another bank (bl=4) clk command a0-9,11 a10 ba0-1 dq d b 0 d b 1 d b 2 d b 3 write y a 1 00 d a0 d a1 write y b 0 10 bl t wr trp act xa xa 00 interrupted auto-precharge activate writea interrupted by read to another bank (cl=2, bl=4) clk command a0-9,11 a10 ba0-1 dq write y a 1 00 d a0 d a1 read y b 0 10 bl t wr trp act xa xa 00 interrupted auto-precharge activate qb0 qb1 qb2 qb3
feb . '00 mitsubishi lsis mitsubishi electric sdram (rev.3.2) 64 m synchronous dram m2v64s20dtp-6,-6l,-7,-7l,-8,-8l (4-bank x 4,194,304 -word x 4-bit) (4-bank x 2,097,152-word x 8-bit) (4-bank x 1,048,576 -word x 16-bit) m2v64s30dtp-6,-6l,-7,-7l,-8,-8l m2v64s40dtp-6,-6l,-7,-7l,-8,-8l 26 [ read with auto-precharge interrupted by read to another bank ] burst read with auto-precharge can be interrupted by read to a nother bank . next act comand can be issued after (bl+trp) from the reada. auto-precharge interruption by a command to the same bank is inhibited. read a interrupted by read to another bank (cl=2, bl=4) clk command a0-9,11-12 a10 ba0-1 dq read y a 1 00 q a0 q a1 read y b 0 10 bl trp act xa xa 00 interrupted auto-precharge activate qb0 qb1 qb2 qb3 full page burst full page burst length is available for only the sequential burst type. full page burst read or write is repeated untill a precharge or a burst terminate command is issued. in case of the full page burst, a read or write with auto-precharge command is illegal. single write when sigle write mode is set, burst length for write is always one, independently of burst length defined by (a2-0).
feb . '00 mitsubishi lsis mitsubishi electric sdram (rev.3.2) 64 m synchronous dram m2v64s20dtp-6,-6l,-7,-7l,-8,-8l (4-bank x 4,194,304 -word x 4-bit) (4-bank x 2,097,152-word x 8-bit) (4-bank x 1,048,576 -word x 16-bit) m2v64s30dtp-6,-6l,-7,-7l,-8,-8l m2v64s40dtp-6,-6l,-7,-7l,-8,-8l 27 auto refresh single cycle of auto-refresh is initiated with a refa (/cs= /ras= /cas= l, /we= /cke= h) command. the refresh address is generated internally. 4096 refa cycles within 64ms refresh 64mbit memory cells. the auto-refresh is performed on 4 banks concurrently. before performing an auto- refresh, all banks must be in idle state. auto-refresh to auto-refresh interval is minimum trfc. any command must not be issued before trfc from the refa command. auto-refresh clk /cs /ras /cas /we cke a0-11 ba0-1 auto refresh on all banks nop or deselect auto refresh on all banks minimum trfc
feb . '00 mitsubishi lsis mitsubishi electric sdram (rev.3.2) 64 m synchronous dram m2v64s20dtp-6,-6l,-7,-7l,-8,-8l (4-bank x 4,194,304 -word x 4-bit) (4-bank x 2,097,152-word x 8-bit) (4-bank x 1,048,576 -word x 16-bit) m2v64s30dtp-6,-6l,-7,-7l,-8,-8l m2v64s40dtp-6,-6l,-7,-7l,-8,-8l 28 self refresh self-refresh mode is entered by issuing a refs command (/cs= /ras= /cas= l, /we= h, cke= l). once the self-refresh is initiated, it is maintained as long as cke is kept low. during the self-refresh mode, cke is asynchronous and the only enabled input. all other inputs including clk are disabled and ignored, so that power consumption due to synchronous inputs is saved. to exit the self-refresh, supplying stable clk inputs, asserting desel or nop command and then asserting cke=h. after trfc from the 1st clk edge following cke=h, all banks are in idle state and a new command can be issued, but desel or nop commands must be asserted till then. self-refresh clk /cs /ras /cas /we cke a0-11 ba0-1 self refresh entry self refresh exit x 00 new command minimum trfc for recovery stable clk nop
feb . '00 mitsubishi lsis mitsubishi electric sdram (rev.3.2) 64 m synchronous dram m2v64s20dtp-6,-6l,-7,-7l,-8,-8l (4-bank x 4,194,304 -word x 4-bit) (4-bank x 2,097,152-word x 8-bit) (4-bank x 1,048,576 -word x 16-bit) m2v64s30dtp-6,-6l,-7,-7l,-8,-8l m2v64s40dtp-6,-6l,-7,-7l,-8,-8l 29 clk suspend and power down cke controls the internal clk at the following cycle. figure below shows how cke works. by negating cke, the next internal clk is suspended. the purpose of clk suspend is power down, output suspend or input suspend. cke is a synchronous input except during the self-refresh mode. clk suspend can be performed either when the banks are active or idle. a command at the suspended cycle is ignored. power down by cke clk command cke command cke standby power down active power down pre nop nop nop nop nop nop act dq suspend by cke clk command dq cke write read d0 d1 d2 d3 q0 q1 q2 q3 ext.clk cke int.clk tih tis tih tis
feb . '00 mitsubishi lsis mitsubishi electric sdram (rev.3.2) 64 m synchronous dram m2v64s20dtp-6,-6l,-7,-7l,-8,-8l (4-bank x 4,194,304 -word x 4-bit) (4-bank x 2,097,152-word x 8-bit) (4-bank x 1,048,576 -word x 16-bit) m2v64s30dtp-6,-6l,-7,-7l,-8,-8l m2v64s40dtp-6,-6l,-7,-7l,-8,-8l 30 dqm control dqm(u, l) is a dual functional signal defined as the data mask for writes and the output disable for reads. during writes, dqm(u, l) masks input data word by word. dqm(u, l) to data in latency is 0. during reads, dqm(u, l) forces output to hi-z word by word. dqm(u, l) to output hi-z latency is 2. dqm function clk command dq dqm(u, l) masked by dqm(u, l)=h disabled by dqm(u, l)=h write read d0 d2 d3 q0 q1 q3
feb . '00 mitsubishi lsis mitsubishi electric sdram (rev.3.2) 64 m synchronous dram m2v64s20dtp-6,-6l,-7,-7l,-8,-8l (4-bank x 4,194,304 -word x 4-bit) (4-bank x 2,097,152-word x 8-bit) (4-bank x 1,048,576 -word x 16-bit) m2v64s30dtp-6,-6l,-7,-7l,-8,-8l m2v64s40dtp-6,-6l,-7,-7l,-8,-8l 31 absolute maximum ratings recommended operating conditions (ta=0 ~ 70'c, unless otherwise noted) capacitance (ta=0 ~ 70'c, vdd = vddq = 3.3 0.3v, vss = vssq = 0v, unless otherwise noted) symbol parameter conditions ratings unit vdd supply voltage with respect to vss -0.5 ~ 4.6 v vddq supply voltage for output with respect to vssq -0.5 ~ 4.6 v vi input voltage with respect to vss -0.5 ~ vdd+0.5 v vo output voltage with respect to vssq -0.5 ~ vddq+0.5 v io output current 50 ma pd power dissipation ta = 25 'c 1000 mw topr operating temperature 0 ~ 70 'c tstg storage temperature -65 ~ 150 'c symbol parameter limits unit min. typ. max. vdd supply voltage 3.0 3.3 3.6 v vss supply voltage 0 0 0 v vddq supply voltage for output 3.0 3.3 3.6 v vssq supply voltage for output 0 0 0 v vih *1 high-level input voltage all inputs 2.0 vdd+0.3 v vil *2 low-level input voltage all inputs -0.3 0.8 v vi=1.4v f=1mhz vi=200mvrms unit test condition parameter symbol pf pf pf pf 6.5 4.0 3.5 2.5 3.8 2.5 3.8 2.5 max. min. input capacitance, i/o pin ci/o input capacitance, clk pin ci(k) input capacitance, control pin ci(c) input capacitance, address pin ci(a) limits notes) 1. vih(max)=5.5v ac for pulse width less than 10ns. 2. vil(min)=-1.0v ac for pulse width less than 10ns.
feb . '00 mitsubishi lsis mitsubishi electric sdram (rev.3.2) 64 m synchronous dram m2v64s20dtp-6,-6l,-7,-7l,-8,-8l (4-bank x 4,194,304 -word x 4-bit) (4-bank x 2,097,152-word x 8-bit) (4-bank x 1,048,576 -word x 16-bit) m2v64s30dtp-6,-6l,-7,-7l,-8,-8l m2v64s40dtp-6,-6l,-7,-7l,-8,-8l 32 average supply current from vdd (ta=0 ~ 70'c, vdd = vddq = 3.3 0.3v, vss = vssq = 0v, output open, unless otherwise noted) ac operating conditions and characteristics (ta=0 ~ 70'c, vdd = vddq = 3.3 0.3v, vss = vssq = 0v, unless otherwise noted) symbol parameter test conditions limits min. max. unit voh(dc) vol(dc) ioz i i high-level output voltage (dc) low -level output voltage (dc) off-state output current input current ioh=-2ma iol= 2ma q floating vo=0 ~ vddq vih=0 ~ vddq+0.3v 2.4 0.4 v v a a -5 -5 5 5 note) 1. icc(max) is specified at the output open condition. 2. input signals are changed one time during 30ns. symbol item limits (max.) unit -8 icc1 operating current ma icc2n tclk = 15ns cke = h vih > vcc - 0.2v vil < 0.2v icc2p ma icc4 all bank active tclk = min bl=4, cl=3 -7 organi- zation x4 x8 x16 single bank operation 20 20 x4/x8/x16 2 2 /cs > vcc -0.2v tclk = 15ns cke = l x4/x8/x16 x4 x16 ma ma ma x8 -6 90 75 85 20 2 9 0 trc=min, tclk =min, bl=1 , cl=3 precharge standby current in non power down mode active standby current burst current icc5 trc=min, tclk=min ma auto-refresh current icc2ns c lk = l & cke = h vih > vcc - 0.2v vil < 0.2v all input signals are fixed. x4/x8/x16 ma 15 15 15 icc2ps 1 1 clk = l cke = l x4/x8/x16 ma 1 icc6 self-refresh current 1 1 x4 /x8 /x16 ma 1 cke < 0.2v 130 11 0 11 0 75 x4/x8/x16 icc3ns 2 5 2 5 cke = h, clk=l x4/x8/x16 2 5 icc3n 3 0 30 cke = h, tclk=15ns x4/x8/x16 3 0 ma /cs > vcc -0.2v precharge standby current in power down mode 70 80 70 70 80 70 70 80 70 70 80 70 100 0.5 0.5 0.5 6,7,8 6l,7l,8l
feb . '00 mitsubishi lsis mitsubishi electric sdram (rev.3.2) 64 m synchronous dram m2v64s20dtp-6,-6l,-7,-7l,-8,-8l (4-bank x 4,194,304 -word x 4-bit) (4-bank x 2,097,152-word x 8-bit) (4-bank x 1,048,576 -word x 16-bit) m2v64s30dtp-6,-6l,-7,-7l,-8,-8l m2v64s40dtp-6,-6l,-7,-7l,-8,-8l 33 ac timing requirements (ta=0 ~ 70'c, vdd = vddq = 3.3 0.3v, vss = vssq = 0v, unless otherwise noted) input pulse levels: 0.8v to 2.0v input timing measurement level: 1.4v ac timing is referenced to the input signal crossing through 1.4v. clk signal 1.4v 1.4v symbol parameter limits unit -7 -8 min. max. min. max. tclk clk cycle time cl=2 10 13 ns cl=3 10 10 ns tch clk high pulse width 3 3 ns tcl clk low pulse width 3 3 ns tt transition time of clk 1 10 1 10 ns tis input setup time (all inputs) 2 2 ns tih input hold time (all inputs) 1 1 ns trc row cycle time 70 70 ns trcd row to column delay 20 20 ns tras row active time 50 1 00k 50 1 00k ns trp row precharge time 20 20 ns twr write recovery time 12 12 ns trrd act to act delay 20 20 ns trsc mode register set cycle time 10 1 0 ns tref refresh interval time 64 64 ms min. max. 10 2.5 1 10 1.5 0.8 67.5 20 45 1 00k 20 12 15 10 64 -6 7.5 2.5 trfc refresh cycle time 8 0 8 0 ns 75
feb . '00 mitsubishi lsis mitsubishi electric sdram (rev.3.2) 64 m synchronous dram m2v64s20dtp-6,-6l,-7,-7l,-8,-8l (4-bank x 4,194,304 -word x 4-bit) (4-bank x 2,097,152-word x 8-bit) (4-bank x 1,048,576 -word x 16-bit) m2v64s30dtp-6,-6l,-7,-7l,-8,-8l m2v64s40dtp-6,-6l,-7,-7l,-8,-8l 34 switching characteristics (ta=0 ~ 70 ' c, vdd = vddq = 3.3 0.3v, vss = vssq = 0v, unless otherwise noted) switching characteristics output load condition (ta=0 ? 70 ' c, vdd= vddq= 3.3 0.3v, vss= vssq= 0v, unless otherwise noted ) note) 1. if clock rising time is longer than 1ns, (tr /2 ? 0.5ns) should be added to the parameter. v out 50pf output timing measurement reference point clk 1.4v 1.4v dq symbol parameter limits unit -7 -8 min. max. min. max. tac access time from clk cl=2 6 7 ns cl=3 6 6 ns toh output hold time from clk 3 3 ns tolz delay, output low- impedance from clk 0 0 ns tohz delay, output high- impedance from clk 2.7 6 3 6 ns note *1 -6 min. max. 6 3 0 3 5.4 5.4 tohz tac clk dq 1.4v 1.4v toh tolz cl=2 cl=3 3 3 ns 2.7
feb . '00 mitsubishi lsis mitsubishi electric sdram (rev.3.2) 64 m synchronous dram m2v64s20dtp-6,-6l,-7,-7l,-8,-8l (4-bank x 4,194,304 -word x 4-bit) (4-bank x 2,097,152-word x 8-bit) (4-bank x 1,048,576 -word x 16-bit) m2v64s30dtp-6,-6l,-7,-7l,-8,-8l m2v64s40dtp-6,-6l,-7,-7l,-8,-8l 35 burst write (single bank) [bl=4] clk /cs /ras /cas /we cke dqm a0-8 a10 a9,11 ba0,1 dq 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 x x x 0 y 0 d0 d0 d0 d0 0 x y x x 0 0 d0 d0 d0 d0 0 trc t rcd tras twr trp trcd twr it alic paramater shows minimum case act#0 write#0 pre#0 act #0 write#0 pre#0
feb . '00 mitsubishi lsis mitsubishi electric sdram (rev.3.2) 64 m synchronous dram m2v64s20dtp-6,-6l,-7,-7l,-8,-8l (4-bank x 4,194,304 -word x 4-bit) (4-bank x 2,097,152-word x 8-bit) (4-bank x 1,048,576 -word x 16-bit) m2v64s30dtp-6,-6l,-7,-7l,-8,-8l m2v64s40dtp-6,-6l,-7,-7l,-8,-8l 36 burst write (multi bank) [bl=4] clk /cs /ras /cas /we cke dqm a0-8 a10 a9,11 ba0,1 dq 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 x x x 0 y 0 d0 d0 d0 d0 0 x y x x 0 0 d0 d0 d0 d0 0 trc t rcd tras twr trp trcd twr it alic paramater shows minimum case act#0 write#0 pre#0 act #0 write#0 pre#0 x x x 1 act#1 trrd trcd y 1 d1 d1 d1 d1 writea#1 ( auto-precharge) act#1 x x x 1 trc
feb . '00 mitsubishi lsis mitsubishi electric sdram (rev.3.2) 64 m synchronous dram m2v64s20dtp-6,-6l,-7,-7l,-8,-8l (4-bank x 4,194,304 -word x 4-bit) (4-bank x 2,097,152-word x 8-bit) (4-bank x 1,048,576 -word x 16-bit) m2v64s30dtp-6,-6l,-7,-7l,-8,-8l m2v64s40dtp-6,-6l,-7,-7l,-8,-8l 37 burst read (single bank) [cl=2, bl=4] clk /cs /ras /cas /we cke dqm a0-8 a10 a9,11 ba0,1 dq 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 x x x 0 y 0 q 0 q 0 q 0 q 0 0 x y x x 0 0 q 0 q 0 q 0 q 0 0 trc t rcd tras trp trcd it alic paramater shows minimum case act#0 read #0 pre#0 act #0 read #0 pre#0 tras
feb . '00 mitsubishi lsis mitsubishi electric sdram (rev.3.2) 64 m synchronous dram m2v64s20dtp-6,-6l,-7,-7l,-8,-8l (4-bank x 4,194,304 -word x 4-bit) (4-bank x 2,097,152-word x 8-bit) (4-bank x 1,048,576 -word x 16-bit) m2v64s30dtp-6,-6l,-7,-7l,-8,-8l m2v64s40dtp-6,-6l,-7,-7l,-8,-8l 38 burst read (multi bank) [cl=2, bl=4] clk /cs /ras /cas /we cke dqm a0-8 a10 a9,11 ba0,1 dq 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 x x x 0 y 0 q 0 q 0 q 0 q 0 1 x y x x 0 0 q 0 q 0 q 0 q 0 0 trc t rcd trcd it alic paramater shows minimum case act#0 reada #0 reada #1 act #0 read #0 pre#0 x x x 1 trrd act#1 y q 1 q 1 q 1 q 1 trcd x x x 1 act #1 trc tras
feb . '00 mitsubishi lsis mitsubishi electric sdram (rev.3.2) 64 m synchronous dram m2v64s20dtp-6,-6l,-7,-7l,-8,-8l (4-bank x 4,194,304 -word x 4-bit) (4-bank x 2,097,152-word x 8-bit) (4-bank x 1,048,576 -word x 16-bit) m2v64s30dtp-6,-6l,-7,-7l,-8,-8l m2v64s40dtp-6,-6l,-7,-7l,-8,-8l 39 write interrupted by write [bl=4] clk /cs /ras /cas /we cke dqm a0-8 a10 a9,11 ba0,1 dq 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 x x x 0 y 0 d 0 d 0 d 0 d 0 1 y 0 d 0 d 0 d 0 d 0 0 t rcd it alic paramater shows minimum case act#0 write #0 write #0 pre#0 x x x 1 trrd act#1 y d0 d 1 d 1 d 1 x x x 1 act #1 y 0 write #0 writea # 1 interrupt same bank interrupt other bank interrupt other bank twr
feb . '00 mitsubishi lsis mitsubishi electric sdram (rev.3.2) 64 m synchronous dram m2v64s20dtp-6,-6l,-7,-7l,-8,-8l (4-bank x 4,194,304 -word x 4-bit) (4-bank x 2,097,152-word x 8-bit) (4-bank x 1,048,576 -word x 16-bit) m2v64s30dtp-6,-6l,-7,-7l,-8,-8l m2v64s40dtp-6,-6l,-7,-7l,-8,-8l 40 read interrupted by read [cl=2, bl=4] clk /cs /ras /cas /we cke dqm a0-8 a10 a9,11 ba0,1 dq 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 x x x 0 y 0 q 0 q 0 1 y 0 q 1 q1 q0 q 0 t rcd it alic paramater shows minimum case act#0 read#0 read #0 x x x 1 trrd act#1 y q 0 q 1 q 1 q 1 x x x 1 act #1 y 1 read#1 reada #1 interrupt other bank trcd interrupt same bank interrupt other bank q0 q 0
feb . '00 mitsubishi lsis mitsubishi electric sdram (rev.3.2) 64 m synchronous dram m2v64s20dtp-6,-6l,-7,-7l,-8,-8l (4-bank x 4,194,304 -word x 4-bit) (4-bank x 2,097,152-word x 8-bit) (4-bank x 1,048,576 -word x 16-bit) m2v64s30dtp-6,-6l,-7,-7l,-8,-8l m2v64s40dtp-6,-6l,-7,-7l,-8,-8l 41 write interrupted by read, read interrupted by write [cl=2, bl=4] clk /cs /ras /cas /we cke dqm a0-8 a10 a9,11 ba0,1 dq 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 x x x 0 y 0 d 0 d 0 y 1 d 1 d 1 d 1 d 1 1 trcd it alic paramater shows minimum case act#0 write #0 write #1 pre#1 x x x 1 trrd act#1 q1 q1 y 1 twr read#1 trcd
feb . '00 mitsubishi lsis mitsubishi electric sdram (rev.3.2) 64 m synchronous dram m2v64s20dtp-6,-6l,-7,-7l,-8,-8l (4-bank x 4,194,304 -word x 4-bit) (4-bank x 2,097,152-word x 8-bit) (4-bank x 1,048,576 -word x 16-bit) m2v64s30dtp-6,-6l,-7,-7l,-8,-8l m2v64s40dtp-6,-6l,-7,-7l,-8,-8l 42 write / read terminated by precharge [cl=2, bl=4] clk /cs /ras /cas /we cke dqm a0-8 a10 a9,11 ba0,1 dq 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 x x x 0 y 0 d 0 d 0 y 0 q0 q0 0 trcd it alic paramater shows minimum case act#0 write #0 read #0 pre#0 0 pre#0 twr x x x 0 act#0 trp 0 tras trcd trp x x x act#0 trc terminate terminate
feb . '00 mitsubishi lsis mitsubishi electric sdram (rev.3.2) 64 m synchronous dram m2v64s20dtp-6,-6l,-7,-7l,-8,-8l (4-bank x 4,194,304 -word x 4-bit) (4-bank x 2,097,152-word x 8-bit) (4-bank x 1,048,576 -word x 16-bit) m2v64s30dtp-6,-6l,-7,-7l,-8,-8l m2v64s40dtp-6,-6l,-7,-7l,-8,-8l 43 write / read terminated by burst terminate [cl=2, bl=4] clk /cs /ras /cas /we cke dqm a0-8 a10 a9,11 ba0,1 dq 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 x x x 0 y 0 d 0 d 0 y 0 q0 q0 0 trcd it alic paramater shows minimum case act#0 write #0 read #0 term pre#0 y 0 term d 0 d 0 d 0 d 0 write#0 twr
feb . '00 mitsubishi lsis mitsubishi electric sdram (rev.3.2) 64 m synchronous dram m2v64s20dtp-6,-6l,-7,-7l,-8,-8l (4-bank x 4,194,304 -word x 4-bit) (4-bank x 2,097,152-word x 8-bit) (4-bank x 1,048,576 -word x 16-bit) m2v64s30dtp-6,-6l,-7,-7l,-8,-8l m2v64s40dtp-6,-6l,-7,-7l,-8,-8l 44 single write burst read [cl=2, bl=4] clk /cs /ras /cas /we cke dqm a0-8 a10 a9,11 ba0,1 dq 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 x x x 0 y 0 d 0 q 0 q 0 t rcd it alic paramater shows minimum case act#0 write #0 read #0 q 0 q 0 y 0
feb . '00 mitsubishi lsis mitsubishi electric sdram (rev.3.2) 64 m synchronous dram m2v64s20dtp-6,-6l,-7,-7l,-8,-8l (4-bank x 4,194,304 -word x 4-bit) (4-bank x 2,097,152-word x 8-bit) (4-bank x 1,048,576 -word x 16-bit) m2v64s30dtp-6,-6l,-7,-7l,-8,-8l m2v64s40dtp-6,-6l,-7,-7l,-8,-8l 45 power-up sequence and intialize clk /cs /ras /cas /we cke dqm a0-8 a10 a9,11 ba0,1 dq 0 it alic paramater shows minimum case pre all refa act #0 mrs refa 0 0 0 ma x x x 200s refa trp trfc minimum 8 refa cycles nop trfc trsc power on
feb . '00 mitsubishi lsis mitsubishi electric sdram (rev.3.2) 64 m synchronous dram m2v64s20dtp-6,-6l,-7,-7l,-8,-8l (4-bank x 4,194,304 -word x 4-bit) (4-bank x 2,097,152-word x 8-bit) (4-bank x 1,048,576 -word x 16-bit) m2v64s30dtp-6,-6l,-7,-7l,-8,-8l m2v64s40dtp-6,-6l,-7,-7l,-8,-8l 46 auto refresh clk /cs /ras /cas /we cke dqm a0-8 a10 a9,11 ba0,1 dq 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 it alic paramater shows minimum case pre all refa y 0 d 0 d 0 d 0 d 0 write#0 x x x 0 act#0 trp trfc trcd all banks must be idle before refa is issued.
feb . '00 mitsubishi lsis mitsubishi electric sdram (rev.3.2) 64 m synchronous dram m2v64s20dtp-6,-6l,-7,-7l,-8,-8l (4-bank x 4,194,304 -word x 4-bit) (4-bank x 2,097,152-word x 8-bit) (4-bank x 1,048,576 -word x 16-bit) m2v64s30dtp-6,-6l,-7,-7l,-8,-8l m2v64s40dtp-6,-6l,-7,-7l,-8,-8l 47 self refresh clk /cs /ras /cas /we cke dqm a0-8, a10 a9,11 ba0,1 dq 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 it alic paramater shows minimum case pre all self refresh entry self refresh exit x x x 0 act#0 trp all banks must be idle before refs is issued. trfc
feb . '00 mitsubishi lsis mitsubishi electric sdram (rev.3.2) 64 m synchronous dram m2v64s20dtp-6,-6l,-7,-7l,-8,-8l (4-bank x 4,194,304 -word x 4-bit) (4-bank x 2,097,152-word x 8-bit) (4-bank x 1,048,576 -word x 16-bit) m2v64s30dtp-6,-6l,-7,-7l,-8,-8l m2v64s40dtp-6,-6l,-7,-7l,-8,-8l 48 clk suspension [cl=2, bl=4] clk /cs /ras /cas /we cke dqm a0-8 a10 a9,11 ba0,1 dq 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 x x x 0 y 0 d 0 q 0 q 0 t rcd it alic paramater shows minimum case act#0 write #0 read #0 q 0 y 0 d 0 d 0 d 0 internal clk suspended q 0 internal clk suspended
feb . '00 mitsubishi lsis mitsubishi electric sdram (rev.3.2) 64 m synchronous dram m2v64s20dtp-6,-6l,-7,-7l,-8,-8l (4-bank x 4,194,304 -word x 4-bit) (4-bank x 2,097,152-word x 8-bit) (4-bank x 1,048,576 -word x 16-bit) m2v64s30dtp-6,-6l,-7,-7l,-8,-8l m2v64s40dtp-6,-6l,-7,-7l,-8,-8l 49 power down clk /cs /ras /cas /we cke dqm a0-8 a10 a9,11 ba0,1 dq 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 it alic paramater shows minimum case pre all act #0 x 0 x x standby power down active power down
feb . '00 mitsubishi lsis mitsubishi electric sdram (rev.3.2) 64 m synchronous dram m2v64s20dtp-6,-6l,-7,-7l,-8,-8l (4-bank x 4,194,304 -word x 4-bit) (4-bank x 2,097,152-word x 8-bit) (4-bank x 1,048,576 -word x 16-bit) m2v64s30dtp-6,-6l,-7,-7l,-8,-8l m2v64s40dtp-6,-6l,-7,-7l,-8,-8l 50 revison history rev. description 1.0 -1st edition date jun '99 2 .0 july '99 -single write mode is added -icc5 for -6 is changed form 110ma to 130ma -trfc is added -trsc is changed 3 .0 -tsrx and tpde are removed oct. '99 3 .1 -twr is changed to 12ns oct. '99
feb . '00 mitsubishi lsis mitsubishi electric sdram (rev.3.2) 64 m synchronous dram m2v64s20dtp-6,-6l,-7,-7l,-8,-8l (4-b a nk x 4,194,304 -word x 4-bit) (4-b a nk x 2,097,152-word x 8-bit) (4-b a nk x 1,048,576 -word x 16-bit) m2v64s30dtp-6,-6l,-7,-7l,-8,-8l m2v64s40dtp-6,-6l,-7,-7l,-8,-8l 51 keep safety first in your circuit designs! mitsubishi electric corporation puts the maximum e ff ort into making semiconductor products better and more reliable, but there is alwa ys the possibilit y that trouble ma y occur with them. trouble with semiconductors ma y lead to personal injur y, f ire or propert y damage. remember to gi v e due consideration to sa f et y when making y our circuit designs, with appropriate measures such as (i) placement o f substituti v e, auxiliar y circuits, (ii) use o f non- f lammable material or (iii) pre v ention against an y m al f unction or mishap. notes regarding these materials 1.these materials are intended as a re f erence to assist our customers in the selection o f the mitsubishi semiconductor product best suited to the customer's application; the y do not con v e y an y license under an y intellectual propert y rights, or an y other rights, belonging to mitsubishi electric corporation or a third part y. 2.mitsubishi electric corporation assumes no responsibilit y f or an y damage, or in f ringement o f an y third- part y 's rights, originating in the use o f an y product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3.all in f ormation contained in these materials, including product data, diagrams, charts, programs and algorithms represents in f ormation on products at the time o f publication o f t hese materials, and are subject to change b y mitsubishi electric corporation without notice due to product impro v ements or other reasons. it is there f ore recommended that customers contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor f or the latest product in f ormation be f ore purchasing a product listed herein. the in f ormation described here ma y c ontain technical inaccuracies or t y pographical errors. mitsubishi electric corporation assumes no responsibilit y f or an y damage, liabilit y, or other loss rising f rom these inaccuracies or errors. please also pa y attention to in f ormation published b y mitsubishi electric corporation b y v arious means, including the mitsubishi semiconductor home page (http://www.mitsubishichips.com). 4.when using an y or all o f the in f ormation contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to e v aluate all in f ormation as a total s yst em be f ore making a f inal decision on the applicabilit y o f the in f ormation and products. mitsubishi electric corporation assumes no responsibilit y f or an y damage, liabilit y or other loss resulting f rom the in f ormation contained herein. 5.mitsubishi electric corporation semiconductors are not designed or manu f actured f or use in a de v ice or s ystem that is used under circumstances in which human li f e is potentiall y at stake. please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor when considering the use o f a product contained herein f or an y speci f ic purposes, such as apparatus or s ystems for tra nsportation, v ehicular, medical, aerospace, nuclear, or undersea repeater use. 6. the prior written appro v al o f mitsubishi electric corporation is necessar y t o reprint or reproduce in whole or in part these materials. 7 .if these products or technologies are subject to the japanese export control restrictions, the y must be exported under a license f rom the japanese go v ernment and cannot be imported into a countr y other than the appro v ed destination. an y di v ersion or reexport contrar y t o the export control laws and regulations o f japan and/or the country o f destination is prohibited. 8.please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor f or f urther details on these materials or the products contained therein.

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